Multifunction terminal circuit

ABSTRACT

A multifunction terminal circuit having an optional circuit (12) a signal terminal (10) connected to the optional circuit; an unidirectional conductor means (14) connected to the signal terminal; and a circuit means (16) whose coupling node (A) is coupled with the signal terminal through the unidirectional conductor means. 
     The circuit means determines a conduction state of the unidirectional conductor means in accordance with a potential difference between the signal terminal and the coupling node.

BACKGROUND OF THE INVENTION

The present invention relates to a multifunction terminal circuit forusing a single terminal for a plurality of uses and, more particularly,to the multifunction terminal circuit which is useful to reduce thenumber of external terminals of an IC package.

Generally, the IC package of the dual in-line type has mountingstandards set up in accordance with the number of the external terminals(external pins). Accordingly, a printed circuit board designed for 24pins, for example, accepts the mounting thereon of a 24-pin type IC madeby any maker. The number of pins of dual in-line ICs are usually 16, 24and 40, for example. The IC package is larger in size as the number ofpins thereof is larger. As a result, the price of each IC rises and itis difficult to make small a circuit block using such ICs. Therefore, itis more desirable to employ a 24-pin type IC package than that of a26-pin type IC package.

Conversely, when the number of pins used is limited, it is desirable touse the external pins as effectively as possible, in order to bringabout many functions of the IC package used. The effective use of theexternal pins is effected by using a proper code conversion and a matrixin an IC memory, for example. In the case of an IC memory model TMM-121Cmanufactured by Toshiba Corporation in which the inventors serve, thememory contents of 512 words are specified by five row data and fourcolumn data. In other words, 512 words are selected by using only 9pins. In fact, there is a case where, although the external pins aremost effectively used by such a circuit technique, the number of thepins must be increased for some function requirements. In such a case,the IC package of 26 pins or more must be used in place of the 24-pinpackage. However, the increase of the number of pins is unacceptable.Therefore it is desirable to form a new type IC device with an expandedfunction and a compatibility with the same type IC device previouslydeveloped. Even in such a case where no compatibility with the olddevice must be taken into account, reduction of the number of externalpins while retaining satisfactory number of functions is very importantfor making the size of the IC small and the cost of it low.

SUMMARY OF THE INVENTION

Accordingly, an object of the invention is to provide a multifunctionterminal circuit in which a single terminal can relay a plurality ofsignals.

To achieve the above object, there is provided a multifunction terminalcircuit comprising an optional circuit, a signal terminal connected tothe optional circuit, an unidirectional conductor means connected to thesignal terminal, and a circuit means whose coupling node is coupled withthe signal terminal through the unidirectional conductor means, forsetting a conduction state of the unidirectional conductor means inaccordance with a potential difference between the signal terminal andthe coupling mode.

A multifunction terminal circuit with such a construction allows thesignal terminal to be used as a signal terminal for the optionalcircuit, and the circuit means (or other circuits connecting to thecircuit means). More specifically, when the unidirectional conductormeans is conductive, the terminal may be used as a signal terminal or apower source terminal for the circuit means. When the unidirectionalconductor means is non-conductive, the signal terminal is used as asignal terminal for the optional circuit. If a plurality of suchmultifunction terminal circuits are collected and the signal terminalsof those terminal circuits are collected together to be treated as asingle terminal, the single terminal can handle two or more differentsignals.

Other objects and features of the invention will be apparent from thefollowing description taken in connection with the accompanyingdrawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a basic construction of a terminalcircuit according to the invention;

FIG. 2 is a block diagram of an EPROM to which the terminal circuitshown in FIG. 1 is applied;

FIG. 3 is a circuit diagram of the detail of the block diagram shown inFIG. 1;

FIGS. 4A to 4F are timing charts for illustrating the operation of theFIG. 3 circuit;

FIGS. 5A to 5C illustrate how the gate threshold voltage Vth of a MOStransistor changes with respect to a source potential Ea relative to asubstrate;

FIG. 6 is a circuit diagram of another example of the detail of theblock diagram shown in FIG. 1;

FIG. 7 shows a block diagram of a modification of FIG. 1 in which asingle terminal 10 is connected to two or more unidirectional conductors14₁, 14₂, . . . ;

FIGS. 8 and 8A are circuit diagrams of modifications of FIG. 3;

FIGS. 9A to 9G are timing charts for illustrating the operation of theFIG. 8 circuit;

FIGS. 10A to 10Q show modifications of the unidirectional conductor 14which are applicable for the circuit of FIG. 3, 6 or 8;

FIG. 11 is a graph showing a voltage-current characteristic of a generaltype P-N junction diode;

FIGS. 12A to 12I show modifications of the first circuit 18 which areapplicable for the circuit of FIG. 3, 6 or 8;

FIGS. 13A to 13D show modifications of the second circuit 20 which areapplicable for the circuit of FIG. 3, 6 or 8;

FIGS. 14A to 14D are circuit diagrams of the circuits when the terminalcircuit according to the invention is applied for the EPROM shown inFIG. 2;

FIGS. 15 to 17 show modifications of the FIG. 3 circuit using CMOStransistors;

FIGS. 18A to 18E are semiconductor cross sectional views forillustrating a manufacturing process of the MOS transistor T14 shown inFIG. 3;

FIG. 19A is an IC cross sectional view of the FIG. 3 circuit formed by aprocess illustrated in FIGS. 18A to 18E;

FIG. 19B is an equivalent circuit of the structure of FIG. 19A;

FIG. 20A is an IC cross sectional view of a modification of FIG. 19A;

FIG. 20B is an equivalent circuit of the structure of FIG. 20A;

FIGS. 21A to 21B show a screening structure for screening the P-Njunction of the MOS transistor T14 part 20 shown in FIG. 19A from therays of light incident thereupon;

FIG. 21C is an equivalent circuit of the structures shown in FIGS. 21Ato 21B;

FIGS. 22A to 22B are a modification of the screening structure shown inFIGS. 21A to 22B;

FIG. 22C is an equivalent circuit of the structure shown in FIGS. 22Aand 22B; and

FIGS. 23A to 23D are structures of the P-N junction diode shown in FIGS.10, 12 and 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of a multifunction terminal circuit according to theinvention will be described in detail referring to the accompanyingdrawings. Throughout the drawings, like or equivalent portions will bedesignated by like reference symbols.

FIG. 1 shows a block diagram of a basic construction of the inventionwhich is directed to the multifunction terminal circuit. In the figure,a signal terminal 10 is connected to an optional circuit 12 including anerasable and electrically programmable read-only memory (EPROM). Theterminal 10 is connected to a coupling node A of a circuit block 16,through an unidirectional conductor 14. The circuit block 16 includes afirst circuit 18 and a second circuit 20. The coupling node A isconnected to the second circuit 20 and is coupled with a first potentialVC by way of the first circuit 18.

Assume now that the potential at the coupling node A is Ea and thepotential at the signal terminal 10 is Eb, and that a signal applied tothe terminal 10 is VP or OE. When Ea≧Eb (=OE), the conductor 14 is innonconductive state. (The maximum potential of the signal OE is normallyVC+about 1 V.) In the nonconductive state of the conductor 14, thecircuit block 16 is electrically disconnected from the terminal 10, sothat only the optional circuit 12 is connected to the terminal 10. Inother words, the terminal 10 is used as an OE signal input terminal ofthe circuit 12. At this time, if the first circuit 18 is conductive, thesecond circuit 20 is rendered conductive by the potential Ea˜VC.Accordingly, the circuit 20 is operable independently of the signal OE.

When Ea<Eb (=VP), the conductor 14 is in conductive state. In this stateof the conductor 14, the circuit block 16 is connected to the terminal10, so that a given potential corresponding to the VP appears at thecoupling node A. At this time, if the first circuit 18 is in an inactivestate, the second circuit 20 is rendered conductive by the givenpotential. Thus, under this condition, the terminal 10 is used as a VPsignal input terminal of the circuit block 16 or the second circuit 20.In this case, the optional circuit 12 need not always respond to thesignal VP. The circuit 12 may optionally be designed so that it respondsto the signal VP or does not so respond.

Let it be emphatically said that the unidirectional conductor 14 allowsa signal to pass unidirectionally in a static sense and not in a dynamicsense. Let us consider now a case that current of 100 μA flows from theterminal 10 to the node A. When the current increases from 100 μA to 200μA without changing the current direction, the change of the currentdirects from the terminal 10 to the node A. On the other hand, when thecurrents decreases from 100 μA to 50 μA, the current change directs fromthe node A to the terminal 10. Thus, when a change of direction of thecurrent flowing through the conductor 14 is taken into account, or whena dynamic signal is handled, the conductor 14 may be bidirectional. Itwill be understood accordingly that the term "unidirectional" is used inthis specification and its appended claims, in the sense of the staticoperation of the circuit, and also that unidirectional does not mean nopassage of a dynamic signal through the conductor 14.

FIG. 2 shows a block diagram of a circuit construction of an EPROM whichis adaptable for the terminal circuit shown in FIG. 1. The circuitconstruction of the EPROM is of the conventional type and accordingly,no explanation of the respective circuit blocks will be given. Forunderstanding the invention, it is sufficient that one knows what partof the overall circuit of the EPROM includes the terminal circuitaccording to the invention when the invention is applied to the EPROM.

The terminal circuit may, for example, be included in a read/program &output enable control logic 100 or an input buffer 102. To write datainto the EPROM, a program signal VP is loaded into the terminal 10.After this, binary data corresponding to the data input is written intoan address of the memory cell array specified by an address input. Thesignal VP used for the data writing or programming is a high voltagepulse of about 25 V, for example. Upon the completion of the datawriting into the memory cell array, the EPROM is used as a normal ROM.For reading out data from the EPROM, the program signal VP is not used.Accordingly, at the time of data read, the terminal 10 may be used as aterminal for handling a signal other than the address input and the datainput signal, for example, an output enable signal OE.

As described above, when the terminal 10 is used for both the signals VPand OE, and the signal VP is handled, a relatively large programmingcurrent flows into the terminal 10. The programming current flowingthrough the EPROM is generally in a range from several tens mA toseveral handreds mA. On the other hand, when the signal OE is handled, asignal current Is flowing into the terminal 10 is extremely small. Thecurrent Is is usually within ±10 μA. When the terminal 10 is used as asignal terminal for a signal such as OE, a large current Is decreasesthe fanout of the remaining circuits connected to the terminal 10. It isfor this reason that, when the terminal 10 is used as a signal terminal,the current Is must be set to be small as possible. As describe above,when the terminal circuit according to the invention is applied to thecontrol logic 100 of the EPROM as shown in FIG. 2 or the buffer 102, theterminal 10 may handle the signal VP going with a large current and thesignal OE with little current.

In such a case, the block construction shown in FIG. 1 may be embodiedby a circuit shown in FIG. 3, for example. Assume now that a groundpotential or a substrate potential is zero and the potential Eb of theterminal 10 and the first potential VC are a positive potential. Theterminal 10 is connected to a VP/OE input terminal of an EPROM 12corresponding to the optional circuit 12 and also to the drain and gateterminals of a MOS transistor corresponding to the unidirectionalconductor 14. The transistor T14 is of the N-channel enhancement typeand the source of the transistor T14 is coupled with the coupling nodeA.

The coupling node A is connected to the potential VC, through thesource-drain path of a MOS transistor T18 corresponding to the firstcircuit 18. The transistor T18 is of the N-channel depletion type, inthis example. The ON/OFF of the transistor T18 depends on a logicallevel of a signal S18 applied to the gate of the transistor. Thecoupling node A is further connected to the drain of an N-channeldepletion type MOS transistor T20₁. The gate and source of thetransistor T20₁ is connected to a substrate, by way of the drain-sourcepath of an N-channel enhancement type MOS transistor T20₂. Thetransistors T20₁ and T20₂ cooperatively form the second circuit 20. Thetransistor T20₁ serves as a load of the transistor T20₂. The ON/OFF ofthe transistor T20₂ depends on a logical level of a signal S20 appliedto the gate thereof. A signal S21 corresponding to the ON/OFF of thetransistor T20₂ is derived from the drain end of the transistor T20₂ oran output node D. The signal S21 is applied as a programming instructionto the VP input terminal of the EPROM 12.

FIGS. 4A to 4F show timing charts useful in explaining the circuitoperation of the circuit shown in FIG. 3. Before time t12, the EPROM 12is used for data read and, after time t12, data is programmed in theEPROM 12. Assume that, before t10, the signal S20 is logical "0" and thesignal S18 is logical "1". At this time, the transistor T20₂ is OFF andthe transistor T18 is ON, and that the gate threshold voltage of thetransistor T14 is Vth and the potential difference Eb-Ea is below Vth,i.e. Eb<Ea+Vth . . . (1). For example, when 0≦Eb≦VC and Ea=VC, theequation (1) is satisfied. At this time, the transistor T14 is OFF.Before time t10, the transistors T14 and T20₂ are OFF while thetransistor T18 is ON, the potential Ea is VC, i.e. Ea=VC. If the VPinput impedance of the EPROM 12 is infinite, when Ea=VC, the potentialof the signal S21 also is VC (=logical "1"). When the potentials Eb andEa (=VC) are too low for a programming input to the EPROM 12, noprogramming is performed, for example, when VC=5 V.

When the signal S20 is logical "1" for a period from t10 to t12, thetransistor T20₂ is ON. Subsequently, the signal S21 becomes zero leveland the potential Ea falls from VC to VC-ΔV. The voltage drop ΔV iscaused by a drain-source conduction resistance of the transistor T18.Even if the potential Ea falls the VC-ΔV, it is possible to satisfy theequation (1). That is, the following relation may be satisfied

    Eb<VC-ΔV+Vth                                         (2)

This is equivalent to the satisfaction of the following relation whenEb=VC

    Vth>ΔV                                               (3)

The relation (3) may be realized by properly selecting pattern sizes ofthe transistors T14, T18, T20₁ and T20₂ in a single IC chip. By properlyselecting the pattern sizes, the potential Ea of the node A may be keptat a substantially constant (≃VC) when the signal S18 is logical "1"(≃VC), regardless of the logic level of the signal S20.

During a period t10 to t12, when the signal S21 is logical "0", theEPROM 12 is ready for read operation. That is, when the output enablesignal OE of logical "0" is applied from the terminal 10 to the EPROM12, the data is read out from a specific address in the EPROM 12. Atthis time, when the transistor T14 is OFF the drain current IP of thetransistor T14 is zero. Accordingly, before time t12 the current (IP+IS)flowing through the terminal 10 is only the OE input terminal current ISof the EPROM 12. If the input impedance at the OE input terminal isinfinite, the current IS is substantially zero. Before t12, only theread operation of data is performed and the terminal 10 is a signalterminal of a high input impedance (low input current) for handling thesignal OE.

After time t12, when the signals S20 and S18 are both logical "0", thetransistors T20₂ and T18 are both OFF. At this time, the potential Eb isVP. If the OFF resistance of each of the transistors T20₂ and T18 andthe VP input terminal resistance of the EPROM 12 are infinite, thevoltage drop across the drain-source path of the transistor T14 is themere gate threshold voltage Vth of the transistor T14. After t12, thepotential Ea becomes VP-Vth, so that the potential of the signal S21becomes VP-Vth. When the potential VP-Vth has a potential levelsatisfactory for the programming input to the EPROM, e.g. VP=25 V, acharge for programming is injected into a memory cell formed of, forexample, a stacked-gate Avalanche injection type MOS (SAMOS), whichmemory cell is located at a given address of the EPROM 12.

After time t14, when the signal S20 becomes logical "1", the transistorT20₂ is turned on. Thereafter, the current IP flows into the transistorT14 and the potential Ea falls from VP Vth to VP-Vth-ΔV while at thesame time the potential of the signal S21 falls from VP-Vth to zero.Following this, the charge injection or the programming to the memorycell (SAMOS) performed during the period t12 to t14, terminates.Incidentally, ΔV is a voltage drop caused by the conduction resistanceof the transistor T14.

FIGS. 5A to 5C show how the threshold voltage Vth of the transistor T14shown by the relation (1) changes with respect to a change of the sourcepotential Ea to the substrate. FIG. 5B shows an Ea vs Vth curve when thepotential difference Eb-Ea is constant. FIG. 5C shows an Eb vs IP whenthe source potential Ea is treated as a parameter. Those figures implythat the substantial threshold voltage Vth of the transistor T14 mayfreely be changed depending on the circuit design or the selection ofthe source potential Ea. The threshold voltage Vth may also be chargedby injecting impurity material into the gate area of the transistor whenit is manufactured. Accordingly, it is possible to design the IC circuitso as to satisfy the relation (1) or (2) when the terminal 10 is used asa signal terminal for the OE signal, as shown in FIG. 3.

Turning now to FIG. 6, there is shown an example where the optionalcircuit 12 includes an internal circuit of CPU etc. 12₂ and the secondcircuit 20 includes a volatile memory device, e.g. a RAM 20₂. In asingle component microcomputer including a volatile memory device suchas a RAM, the contents of the RAM and the other registers are destroyedwhen the power supply is shut off. When such a microcomputer is used,given data must be loaded into the RAM etc. every time the power supplyis turned off and on. As a countermeasure, it is conceivable that a padis additionally provided on the IC chip and the RAM is supplied withpower from another power source. TM_(p) 8048 manufactured by ToshibaCorporation or mode 8048 by Intel Corporation, for example, may be usedas the microcomputer to which such a proposal is applicable. If so done,it is possible to continue the current supply in the RAM even if thepower source of the CPU is turned off. Accordingly, only the RAM isalways supplied with power, so that the contents of the RAM are neverdestroyed even if the CPU etc. is subjected to a power OFF.

The terminal 10 is used as a terminal to handle an interrupt input INT,for example, when the power source VC of the CPU is ON, while, when thepower source VC is OFF, it is used as a power supply terminal forsupplying power to the RAM. The terminal 10 is connected to an extra pad11 on an IC chip (not shown). The pad 11 is connected to the INT inputterminal of an external circuit of CPU 12₂, through an inverter 12₁. Thecircuit 12 is supplied with power from the power source VC. The pad 11is connected to the coupling node A, via the drain-source path ofenhancement type MOS transistors T14₁ and T14₂. The transistors T14₁ andT14₂ are connected at the gates to the drains and the drain-source pathsof the transistors are connected in series.

The coupling node A is connected to the power source VC by way of thesource-drain path of an enhancement type MOS transistor T18. The gate ofthe transistor T18 is connected to the drain thereof. The node A is alsocoupled with the power input of the RAM 20₂, through a depletion-typeMOS transistor T20₁. The transistor T20₁ is connected at the gate to thesource to form a load of the RAM 20₂. The source of the transistor T20₁is an output node D and the node D and/or the node A is used as a powersupply circuit for the other volatile devices.

Assume now that the gate control voltages of the transistors T14₁, T14₂and T18 are Vtha, Vthb and Vthc, and that

    Vtha+Vthb>Vthc                                             (4)

On this assumption, when the power source VC is ON, the circuit 12 issupplied with power from the VC, and the circuit 20 is supplied withpower from the VC, through the transistor T18. At this time, thepotential Ea at the node A is

    Ea=VC-Vthc                                                 (5)

Accordingly, the transistors T14₁ and T14₂ are OFF even if the potentialEb of the terminal 10 is zero or VD (=VC). When VC=VD=5 V, Vtha+Vthb=2 Vand Vthc=1 V, Ea=4 V from the equation (5). The transistors T14₁ andT14₂ are turned on when the following relation is satisfied

    Eb≧Ea+Vtha+Vthb                                     (6)

In the above assumption, to turn on the transistors T14₁ and T14₂ whenEa=4 V, it is necessary that Eb≧4+2=6 V. However, the potential Eb is 5V at its maximum and therefore the transistors T14₁ and T14₂ can not beturned on. Thus, when the transistors T14₁ and T14₂ or theunidirectional conductor 14 is OFF, the current IP is zero. Accordingly,when the power source VC is ON, the terminal 10 may be used as aninterrupt input terminal to the circuit 12₂.

Let us consider a case where the power source VC is turned off. In thiscase, it is assumed that only the terminal 10 is connected to the powersource VD (=5 V). Upon turning off the power source VC, power suppliedto the circuit 12₂ and 18 is stopped, so that VC=0 V and the transistorT18 is OFF. At this time, the potential Ea at the node A falls to avalue to satisfy the equation (6) or when the potential Ea falls from 4V to 3 V, the transistors T14₁ and T14₂ are turned on. As a result, thepotential Ea is clamped at 3 V. At this time, if the voltage drop acrossthe drain-source path of the depletion type transistor T20₁ is 0.5 V,the power supply to the RAM 20₂ is from the potential Ed of 2.5 V. Theremaining volatile devices connected to the nodes A and D are alsocoupled with the potential Ea (3 V) or Ed (2.5 V). Accordingly, thecontents of the volatile devices of the RAM 20₂ are never destroyed whenthe power source VC is turned off. The power supply voltage to the RAM20₂ etc. from the power source VD is lower than that from the powersource VC. Therefore, when the power source VC is OFF or in a stand-bystate, no power is supplied to the circuit 12, so that the powerconsumption of the microcomputer becomes extremely small as a whole.Thus, when the power source VC is OFF, the terminal 10 may be used as apower supply input terminal by the power source VD.

In the example as mentioned above, the unidirectional conductor 14 isformed by a coupled of transistors T14₁ and T14₂ connected in series.However, this may be formed by a single MOS transistor T14. In thiscase, the gate threshold voltage Vthab of the transistor T14 must belarger than the gate threshold voltage Vthc of the transistor T18. IfVthab-Vthc≧1 V, the conductor 14 may be formed by a singleenhancement-type MOS transistor.

FIG. 7 shows a basic construction when a plurality of circuit blocks16₁, 16₂, . . . are coupled with one signal terminal 10. To the terminal10 is connected an optional circuit 12. The terminal 10 is furtherconnected to first and second circuit blocks 16₁ and 16₂, through firstand second unidirectional conductors 14₁ and 14₂. When the conductors14₁ and 14₂ are both in OFF state, the terminal 10 is used as a signalinput terminal to the circuit 12. In an inactive state of the circuit12, when only the first conductor 14₁ enters in a conductive state, theterminal 10 serves as a signal input terminal to the circuit block 16₁.In an inactive state of the circuit 12, when only the second conductor14₂ becomes conductive, the terminal 10 serves as a signal inputterminal to the circuit block 16₂. In this way, the single terminal 10may be used for multiple inputs to a multifunction circuit.

FIGS. 8 and 8A show a modification of the circuit shown in FIG. 3. Inthis example, the circuit block 16 includes a positive feedback (PFB)circuit 19. The output node D is connected through an inverter I19 tothe gate of an N-channel MOS transistor T19₁. The transistor T19₁ isgrounded at the source and connected at the drain to a feedback node Fand to the source of an N-channel MOS transistor T19₂. The gate of thetransistor T19₂ is connected to the terminal 10 and the drain thereof isconnected to the fixed potential VP (FIG. 8) or the signal S21 (FIG.8A). The node F is connected to the gate of the transistor T14 (FIG. 8)or the transistor T14₃ (FIG. 8A). The same node is grounded through thedrain-source circuit of an N-channel enhancement type MOS transistorT19₃ of which the gate is connected to the drain thereof.

FIGS. 9A to 9G are a set of timing charts for illustrating the operationof the circuit shown in FIG. 8 or FIG. 8a. Before time t10, the signalsS20 and S18 are logical "0" and logical "1", respectively. In thislogical state, the transistors T20₂ is OFF while the transistor T18 isON. The gate potential of the transistor T14 (T14₃) or the potential Efof the node F change within an approximate range of 0 to 5 V inaccordance with the signal OE inputted to the gate of the transistorT19₂. The transistor T19₃ discharges the potential near the node Fpotential when the transistor T19₂ is OFF with the logical change"1"→"0" of the signal OE. Thus, the transistor T19₃ holds the node Fpotential near 5 V when the transistor T19₁ is OFF with the signal OE atlogical "1" and the transistor T19₂ ON. For this, the ON-resistance ofthe transistor T19₃ is adequately larger than that of the transistorT19₂. If the relation (1) is satisfied, the transistor T14 (T14₁) isleft OFF. Accordingly, the potential Ea is approximately VC (≃5 V) andthe level of the signal S21 is approximately VC. As a result, theinverter I19 has an output of logical "0" and the transistor T19₁ isOFF.

During the period times t10 to t12, when the signal S20 becomes logical"1", the transistor T20₂ is turned on. Thereafter, the level of thesignal S21 becomes zero and the potential Ea falls from VC to VC-ΔV.When the signal S21 becomes zero level, the output of the inverter I19becomes logical "1" and the transistor T19₁ is turned on. As a result,the potential Ef becomes zero level. Before time t12, the terminal 10 isused as a signal terminal for the signal OE.

During a period t12 to t13, when the signal S20 becomes logical "0", andthe potential Eb rises up to VP, the transistor T20₂ is turned off andthe potential of the signal S21 rises. Thereafter, the output level ofthe inverter I19 falls while the potential Ef rises. The rise of thepotential Ef continues until Ef≃VP. With rising of Ef, the potential Eaalso rises. At this time, the rise of the potential Ea causes thepotential at the node D to also rise, so that the nodes D→F→A→D from aPFB loop. Incidently, the PFB is set up when a signal at the node A isfed back to the node F in phase. When the transistor T20₂ is turned offat time t12, the potential of the signal S21 and the potentials Ea andEf rapidly reach the voltage VP through the action of the PFB. After thePFB operation starts or ends, i.e. at time t13, the signal S18 becomeslogical "0". The transistor S18 is turned off when Ea>VC holds during aperiod of time from t12 to t13 and its OFF state is ensured by thelogical "0" state of the signal S18 after time t13.

During a period from times t13 or t14, the potentials Eb, Ea, Ef and thesignal S21 are VP. During this period, programming of the EPROM 13 isperformed. When the first time programming is completed and the signalS20 becomes logical "1", the transistor T20₂ is turned on. Upon theturning-on of the transistor, the signal S21 falls toward zero leveland, with the falling, the potentials Ef and Ea also fall. The fallingof the potential Ea starts slightly behind that of the signal S21, sothat an instantaneous pulse current IP frequently flows, although thecurrent IP is small. Accordingly, the programming current of the overallEPROM 12 is also small and therefore a current capacity of a PROM writermay be small.

The circuit construction shown in FIG. 8 or FIG. 8A is applicable for,for example, a one-chip IC circuit including CPU, RAM, registers, etc.,as shown in FIG. 6.

FIGS. 10A to 10Q show modifications of the unidirectional conductor 14which are applicable for the circuit shown in FIG. 6 or 8. The examplesshown in FIGS. 10A to 10I and FIG. 10Q are featured in that the ON andOFF states of the conductor 14 depend on the potential difference Eb-Ea.The feature of the FIGS. 10J to 10P resides in that the same states ofthe conductor 14 depend on the potential difference Eb-Ea and/or apotential Eg. The potential Eg may be the potential Ef of FIG. 8 oranother ON/OFF signal or a fixed potential e.g. Ey or Ex to be givenlater.

The examples shown in FIGS. 10A and 10B are featured by the use ofN-channel and p-channel enhancement-type MOS transistors T14. Thesubstrate of the MOS transistor T14 is normally at a ground level or apower source level. By setting the substrate potential to a properpotential, threshold voltage Vth of the MOS transistor T14 may bechanged properly.

The example of FIG. 10C is featured by the use of a single P-N junctionD14 and the example of FIG. 10D has a feature of the use of a pluralityof P-N junctions D14_(n). FIG. 11 shows a voltage vs currentcharacteristic of an usual type P-N junction D14. As seen from FIG. 11,in the case of FIG. 10C, for example, the conductor 14 conducts whenEb≧Ea+Vf. When Ea-Eb<Vbd and Eb<Ea+Vf where Vbd is a breakdown voltageof the P-N junction D14, the conductor 14 is cut off.

FIGS. 10E and 10C show examples where the diode P-N junction is replacedby the base-emitter P-N junction of the bipolar transistor T14. FIG. 10Fshows an example in which a P-N junction (diode) D14 is inserted betweenthe collector and base of the transistor T14 shown in FIG. 10E. Althoughnot shown, the P-N junction D14 may be connected in series with thecollector or emitter of the transistor T14.

FIGS. 10G and 10H show examples where two enhancement type MOStransistors T14₁ and T14₂ are connected in series. The circuit shown inFIG. 10G has already been described relating to FIG. 6. The exampleshown in FIG. 10H corresponds to that where the circuit shown in FIG.10G is formed by using a CMOS.

FIG. 10J shows an example where a switching MOS transistor T14₃ forswitching is connected in series to a MOS transistor T14₁. The sourcepotential (or a prescribed node potential) Ec of the transistor T14₃ isdetermined in accordance with the gate potential Eg of the transistorT14₃. When the gate threshold voltage Vth₃ of the depletion type MOStransistor T14₃ is related by Eb-Vth₃ =Eg, Ec=Eg-Vth₃ holds. From thisrelation, Eb may be larger than Ec, Eb>Ec, since the potential Ec isdetermined by the potential Eg. In other words, the transistor T14₁ isturned on and off in accordance with the magnitude of the potentialdifference Ec-Ea. Therefore, even when the potential Eb shown in FIG.10J is higher than the potential Eb in FIG. 10A, the transistor T14₁ maybe turned off.

FIG. 10K shows an example where an enhancement type MOS transistor T14₁corresponding to the transistor T14 in FIG. 10A is connected in serieswith a depletion type MOS transistor T14₃. The potential Eg is soselected that a relation Eg-Vth₃ <Ea holds. Here, the potential Eb istreated as a signal. The source spotential Ec of the transistor T14₁ isgiven

    Ec=Eg-Vth.sub.3 (where Eb≦Ec+Vth.sub.1)

or

    Ec=Eb-Vth.sub.1 (where Eb>Ec+Vth.sub.1)

Under this condition, no current path continuing from the potential Ecside to the potential Ea side is formed.

The FIGS. 10D, 10F, 10G and 10H examples are useful for increasing thepotential difference Eb-Ea when the conductor 14 is turned on. Theexample of FIG. 10I may adjust the potential difference Eb-Ea. Thepotentials Eb and Ea are applied to the source and drain of a P-channelenhancement-type MOS transistor T14₁, respectively. The drain of thetransistor T14₁ is coupled with a potential Ea, through theseries-connected drain-source circuits of N-channel MOS transistors T14₄and T14₅. The gates of the transistors T14₄ and T14₅ are connected tothe sources thereof, respectively, and the source of the transistor T14₄is connected to the gate of the transistor T14₁. The transistors T14₄and T14₅ are of the depletion type and have conduction resistances R4and R5, respectively.

The potential Ey at the gate of the transistor T14₁ is given by ##EQU1##When the gate threshold voltage of the transistor T14₁ is expressed byVth₁, the transistor T14₁ is turned on when the following relationholds:

    Ey≦Eb+Vth.sub.1                                     (8)

From the relations (7) and (8), we have ##EQU2## The equation (9)implies that the condition for turning on of the transistor T14₁ may bechanged by the resistances R4 and R5. When Ex>Ea, Ey>Ea, the potentialdifference Eb-Ea obtained when the transistor T14₁ is turned onincreases. Conversely, when Ex<Ea, the potential difference Eb-Eabecomes small. The transistors T14₄ and T14₅ may be replaced by anothercircuit for forming a potential divider or a voltage divider.

FIGS. 10L to 10P show switch devices which are applicable mainly for theunidirectional conductor 14 shown in FIG. 8. FIG. 10L corresponds to thetransistor T14 of FIG. 8. FIG. 10M is an example where the enhancementtype MOS transistor T14 of FIG. 10L is replaced by the depletion typeMOS transistor T14.

FIG. 10N shows an example in which an NPN type bipolar transistor T14 isused for the switch device. The example shown in FIG. 10O uses a PNPtransistor T14 in place of the NPN transistor T14 in the circuit shownin FIG. 10N. In this case, the base input signal Eg (or Ef) of thetransistor T14 is an inversion of that of FIG. 10N.

FIG. 10P shows an example using a thyristor TH14 for the switch device.

FIG. 10Q shows an example in which, by conecting in series a P-Njunction diode D14 and a Zener diode ZD14, the potential differenceEb-Ea, which causes the conductor 14 to turn on, is increased.

FIGS. 12A to 12I show modifications of the first circuit 18 which areapplicable for the circuit of FIG. 3, 6 or 8. FIGS. 12A to 12E showcircuits which are applicable for the unidirectional conductor 14. Theexamples shown in FIGS. 12F to 12I are unsuitable for the applicationthereof to the unidirectional conductor 14 but those are applicable forthe first circuit 18. FIGS. 12F to 12I serve as the bidirectionalconductors always or when an operation condition is satisfied. In thecase of FIG. 12F, when a Zener voltage VZ of a zener diode ZD18satisfies a relation VC-Ea≧VZ, current flows from the cathode to theanode. When a forward voltage drop VF satisfies a relation VC-Ea≦-VF,current flows from the anode to the cathode. When VZ≦VC-Ea≦-VF, theZener diode ZD18 is turned off.

The example shown in FIG. 12G uses a depletion-type MOS transistor T18for a load resistor of the second circuit 20. FIG. 12H shows an examplein which a diffusion resistor R18 is used as the load resistor. Theexample of FIG. 12H is formed in a semiconductor substrate by diffusingN⁺ or P⁺ impurity thereinto. The examples shown in FIGS. 12G and 12H areperfect bidirectional conductors. For this, when the circuit shown inFIG. 12G or 12H is used, if the transistor T14 is turned on in FIG. 3,for example, the current IP flows to the potential VC side. In otherwords, the terminal 10 is coupled with the potential VC. When a circuitis so designed that such a coupling provides no problem, the firstcircuit 18 shown in FIG. 12G and 12H may be used.

FIG. 12I shows an example having a function of the combination of thecircuits FIGS. 12F and 12H. When VC<Ea, the circuit of FIG. 12Icorresponds to a parallel circuit of the resistor R18 of FIG. 12H and aZener dioe ZD18 of FIG. 12F. When the base-emitter threshold voltage Vbeof the transistor T18 satisfies a relation VC-Ea≧(1+R18₁ /R18₂) Vbe, thetransistor T18 is turned on. When the above relation is not satisfied,the transistor T18 is OFF. The examples shown in FIG. 12F or 12I areused when the potential difference VC-Ea is desired to be clamped at afixed value.

FIGS. 13A to 13D show modifications of the second circuit 20 which areapplicable for the circuit shown in FIG. 3, 6 or 8. Those circuits aregenerally called a 3-state buffer or a tristate buffer. FIGS. 13A and13B show inverted buffers and FIG. 13C is a non-inverted buffer. FIG.13D is a transfer gate. When such a 3-state buffer is used, the couplingnode A may be separated from the signal S20, S21 or S21 and/or theground circuit independently of the logical level of the signal S20.

FIGS. 14A to 14D show specific circuit diagrams when the terminalcircuit according to the invention is applied for the EPROM shown inFIG. 2. FIGS. 14A to 14D show the substantial parts of the block diagramshown in FIG. 2. Those drawings are used to illustrate how the terminalcircuit is connected to the EPROM. The circuit construction of the EPROMis not essential to the invention and is not the subject matter of theinvention. Accordingly, the substantial parts thereof will be describedwithout referring to the circuit of it.

The terminal circuit is included in an input buffer 102 shown in FIG.14A. The signal terminal 10 is connected to the VP/OE inputs of anoutput enable logic circuit 100 shown in FIG. 14C and the input buffer102. A signal R/PM (S18) inputted to a transistor T18 of the terminalcircuit switches between a read mode of the EPROM and a program mode. Asignal R/PM is an inversion of the signal R/PM in its level. The EPROMis in the read mode when the R/PM is logical "1" and is in the programmode when it is logical "0".

When the R/PM=logical "0", the program signal VP, e.g. 25 V, is appliedto the terminal 10. The VP/OE=25 V is detected as VP/OE=logical "1" inthe output enable logic 100. Upon the detection of the VP/OE, the logic100 produces signals E="0" and E="1" and toward an output buffer 104.Then, nodes N1 and N2 within the buffer 104 become logical "0" and theN-channel MOS transistors T104₁ and T104₂ are cut off. The cutting offof the transistors causes a node N3, which for provides a data outputDO1, to have a high impedance.

A signal PC inputted to an N-channel MOS transistor T20₃ of the terminalcircuit is normally logical "1". After a given time (e.g. 1μ second)lapses since programming input data DI1 is inputted, the signal PC islogical "0" only for a time, e.g. 50 m second, taken for theprogramming. When PC="0", the DI1 with a given logical level ("0" or"1") is applied as a signal S21 to the gate of an N-channel MOStransistor T102₁. The transistor T102₁ is turned on when the signal S21is logical "1" and is turned off when it is logical "0". The logicallevel "1" of the signal S21 corresponds to the potential VC in the readmode and to the potential VP-Vth in the program mode, as shown in FIG.4E.

When R/PM="0", R/PM="1" and PC="0", i.e. in the program mode, ifDI1="0", a signal S20 inputted to an N-channel MOS transistor T20₂ ofthe terminal circuit is logical "0" and the transistor T20₂ is turnedoff. As a result, the signal S21 is logical "1" or the potential VP-Vth(≃23 V) and the potential VP is applied through the transistor T102₁ toa column gating 106 shown in FIG. 14B. The potential VP inputted to thecolumn gating 106 is applied to a given cell in a memory cell array 108,so that data write or programming is performed. The address of the givencell is determined by a row decoder 112 and a column decoder 110.

In the read mode, R/PM="1", R/PM="0" and PC="1". As a result, thetransistor T20₃ is turned on and the signal S21 is logical "0"regardless of the logical level of the data DI1, and the transistorT102₁ is turned off. In the read mode, the potential Ea at the couplingnode A is in the vicinity of VC (see FIG. 4D). Accordingly, when thepotential Eb of the VP/OE inputted to the terminal 10 satisfies therelation (1), an N-channel MOS transistor T14 is in OFF state and thedrain current IP of the transistor T14 is zero. At this time, VP/OEserves as an output enable signal OE. Accordingly, the logical states ofthe signal E and the signal E at the logic 100 are determined by alogical state of the signal VP/OE. Depending on the logical statedetermined, it is decided whether the node N3 of the output buffer 104is set to a high impedance or the buffer 104 produces output data DO1.

FIG. 14D shows the row decoder 112. In the program mode, R/PM="0" andthe signal S21 with the potential corresponding to VP-Vth or logical "1"appears at the node D of the terminal circuit. The potential VP-Vth isapplied to the gates of N-channel MOS transistors T112₁ to T112_(i) ofthe row decoder 112. The logical levels on row lines r₁ to r_(i)continuous to the decoder 112 are determined by the logical levels atnodes M₁ to M_(i). The logical levels at the nodes M₁ to M_(i) aredetermined by a set of address inputs (R₀, R₁, . . . R_(i)). Forexample, when R₀ ="1", R₁ . . . R_(i) ="0", only the node M₁ becomeslogical "1", so that the programming potential (≃VP) is applied to onlythe row line r₁, through the transistor R112₁. Similarly, when only thefirst column line of the array 108 becomes logical "1" (≃VP), data isloaded into the memory cell located at a crosspoint of the first columnline and the row line r₁.

In the read mode, R/PM="1" and the signal S21 is logical "0", so thatthe transistors T112₁ to T112_(i) are all turned off. In this case, therow lines r₁ to r_(i) have logical levels according to the set of theaddress inputs (R₀, R₁, . . . R_(i)). The logical "1" at this time isapproximately VC level. Incidentally, the column decoder 110 may beexactly the same as that of the row decoder 112.

FIGS. 15 to 17 show circuit diagrams in which the circuit shown in FIG.1 is formed in terms of a CMOS transistor circuit using a P-substrate.It may of course be formed by the CMOS transistor circuit with anN-substrate. In the case of FIG. 15, an N-channel enhancement-type MOStransistor T14 forms the unidirectional conductor 14. The first circuit18 is formed by a P-channel enhancement-type MOS transistor T18 and thesecond circuit 20 by a CMOS inverter.

In the case of use of the CMOS inverter 20, when a load impedancecoupled with the output node D is sufficiently large, the currentflowing from the coupling node A into a power supply circuit of theinverter 20 is nearly zero. Accordingly, when the FIG. 3 circuit isreplaced by the FIG. 15 circuit, the current IP at the time ofprogramming may be extremely small.

In the circuit in FIG. 16, a P-channel enhancement-type MOS transistorT14 forms the unidirectional conductor 14. The first circuit 18 isconstructed by a buffer circuit 18 connected in series to two CMOSinverters. The second circuit 20 is constructed by an N-channelenhancement-type MOS transistor T20. In FIG. 16, two nodes eachcorresponding to the coupling node A shown in FIG. 1 are provided: oneis a first coupling node A connecting the gate of the transistor T20with the output terminal of the circuit 18; the other is a secondcoupling node A coupling the drain of the transistor T20 with the drainof the transistor T14. The unidirectional conductor 14 is turned offwhen the gate threshold voltage Vth of the transistor T14 satisfies therelation (1), i.e. Eb-Ea<|Vth|. Accordingly, with relation to an ON/OFFstate of the conductor 14, the first coupling node A corresponds to thenode A of FIG. 1. In the example shown in FIG. 16, the transistors T14and T20 form a CMOS inverter and the current IP is nearly zeroregardless of the logical level of the node A.

In FIG. 17, the unidirectional conductor 14 is formed by a seriescircuit having a P-channel enhancement-type MOS transistor T14 and a P-Njunction diode D14. The first circuit 18 is formed by a CMOS buffercircuit like that of FIG. 16. The second circuit 20 is formed by a CMOSinverter 20 including a P-N junction diode D20 related to the draincircuit thereof in series fashion. When the input signal S18 (R/PM) ofthe circuit 18 is logical "1", Ea=Eb=VC and the transistor T14 is OFF.At this time, the logical level "1" or "0" of the second coupling node Acoupled with the cathode of the diode D14 is determined by logical level"0" or "1" of a signal S21 applied to the inverter 20. When the signalS18 is logical "0" Eb=VP, the transistor T14 is turned on. At this time,the logical level "1" or "0" at the node A becomes VP or zero. The diodeD14 prevents a reverse current IP from flowing from the node A to theterminal 10 when the logical levels at the nodes A and A are bothlogical "1". The diode D20 prevents part of the current IP from flowingfrom the terminal 10 to the VC, through the transistor T20₂ when Eb=VP,S21=logic "0" of the trasistor T20₂ =ON. That is, the diodes D14 and D20are used as reverse current stoppers.

FIGS. 18A to 18E show a series of semiconductor cross sectional viewsfor illustrating a manufacturing process of the transistor T14 shown inFIG. 3. The manufacturing process to be given is correspondingly appliedto the manufacture of other transistors T18, T20₁ and T20₂.

In FIG. 18A, an SiO₂ layer 202 is grown on a P type substrate 200. AnSi₃ N₄ layer 204 is layered at a given region on the layer 202. On thislocation, a gate, a drain and a source of the transistor T14 is formedlater. Boron 206 for channel cutting is implanted into the field regionon the periphery of the layer 204 by the ion implantation.

In a step of FIG. 18B, the layer 202 of the field region is thickened bythe thermal oxidation. After the thickening step of the layer 202 ends,the layer 204 is removed.

In a step of FIG. 18C, a gate oxide film 203 is formed on the channelregion within the given region after the removal of the layer 204.

Then, given impurity 208 is implanted thereinto by the ion implantation,in order to control the gate threshold voltage Vth of the transistorT14. The given impurity 208 may be boron (IIIA group element), forexample, for the enhancement type and phosphorus or arsenic (VA groupelement), for example, for the depletion type. After the implantation ofthe impurity 208 is completed, polysilicon (or molybdenum) 210 islayered as a gate electrode.

In a step of FIG. 18D, the oxide layer 203 is removed from the regionwhere the drain, the source and an N⁺ wiring layer are formed. Then, N⁺impurity is diffused through the oxide-layer removed region thereby toform N⁺ regions 212₁ and 212₂.

In a final step of FIG. 18E, an SiO₂ layer 202 is further formed so asto cover the N⁺ regions 212₁ and 212₂, and the polysilicon 210. Then,parts of the SiO₂ layer 202 on the polysilicon 210 and the N⁺ regions212₁ and 212₂ are opened, and through the opening metal-wiring layers214₁ and 214₂ made of aluminum, for example, are formed.

FIG. 19A shows an IC cross sectional view of the FIG. 3 circuitmanufactured through the process illustrated in FIGS. 18A to 18E. FIG.19B is an equivalent circuit of the structure shown in FIG. 19A.

FIG. 20A is a modification of the structure of FIG. 19A, and FIG. 20B isan equivalent circuit of the structure of FIG. 20A. The example shown inFIGS. 20A and 20B corresponds to an example which is the combination ofthe circuits of FIG. 10D and FIG. 12B, and the second circuit or theCMOS inverter 20 of FIG. 15. The structure of FIG. 20A may be formed bya conventional CMOS manufacturing process. The circuits shown in FIGS.3, 6, 8, 10A to 10Q, 12A to 12I, 13A to 13D, 14A to 14D, and 15 to 17may be integrated by the process referred to relating to FIGS. 18A to18E or another proper conventional process.

FIGS. 21A to 21B structurally illustrate the MOS transistor used in thecircuit shown in FIG. 19A of which the IC structure is for preventingphotocurrent. In the IC device which is exposed to light rays through atransparent cover, such as EPROM to erase the stored contents byultraviolet rays, light rays are incident upon the P-N junction of theIC exteriorly. The P-N junction illuminated by exterior light raysproduces photocurrent. Accordingly, when exterior light rays impingeupon the P-N junction formed by the P-substrate 200 and the N⁺ region212₂, IP≠0, even when the transistor T14 is in the OFF state. As aresult, in the case where another circuit (not shown) connecting to theterminal 10 of FIG. 3 is a device of which the maximum output current issmall, such as an CMOS, the fan-out of the other circuits becomessubstantially small. Further, when the current IP arising from thephotocurrent is large, the normal operation in the other circuits areadversely affected.

In order to prevent the photocurrent, the example shown in FIG. 12Acovers the P-N junctions formed between the substrate 200 and the region212₁, and the substrate 200 and the region 212₂ with metal patterns 214₁and 214₂ made of aluminum, for example. The covering patterns 214₁ and214₂ substantially shade the light from the P-N junctions, so that thephotocurrent is almost zero.

FIGS. 22A to 22C are a modification of the example shown in FIGS. 21A to21C. In the example, the P-N junction between the N⁺ region 212₁ and theP-substrate 200 is covered with a second polysilicon 210₂.

The shading structure of FIGS. 21A to 21C or 22A to 22C may be appliedfor screening the P-N junction device other than the MOS transistor T14from the light. Any other suitable screening structure may be employedfor such a purpose if the screening structure can cover the P-N junctionwith light screening material.

FIGS. 23A to 23D show some examples of the P-N junctions shown in FIGS.10, 12 and 17. Those are other example than diodes D14, D14₂, and D18shown in FIG. 20A. FIG. 23A shows an example where a P-N junction isarranged on a sapphire substrate 200 laterally. FIG. 23B shows anexample in which a P-N junction of polysilicon on an SiO₂ layer 202 isformed on a P-substrate 200. In an example shown in FIG. 23C, a P-Njunction of polysilicon is arranged on the layer 202 of FIG. 23Bvertically. FIG. 23D shows an example where an N⁺ region is formed in aP-substrate 200 by diffusion and a P-polysilicon layer is formed thereonthereby to form a P-N junction.

Although specific constructions have been illustrated and describedherein, it is not intended that the invention be limited to the elementsand constructions disclosed. One skilled in the art will recognize thatthe particular elements or subconstructions may be used withoutdeparting from the scope and spirit of the invention.

What we claim is:
 1. A multifunction terminal circuit, comprising:a. anoptional circuit; b. a signal terminal connected to said optionalcircuit as an input terminal for said optional circuit; c.unidirectional conductor means also connected to said signal terminalfor unidirectionally passing both signals and supply power applied tosaid signal terminal; and d. circuit means, having a coupling nodecoupled to said signal terminal through said unidirectional conductormeans, for setting the conduction state of said unidirectional conductormeans in accordance with a potential difference between said signalterminal and said coupling node;wherein, when said unidirectionalconductor means is rendered conductive, said signal terminal operates asan input terminal to said circuit means for either signals or supplypower being applied to said signal terminal, and when saidunidirectional conductor means is rendered non-conductive, said signalterminal operates as an input terminal to said optional circuit forsignals being applied to said signal terminal.
 2. A multifunctionterminal circuit, comprising:a. an optional circuit; b. a signalterminal connected to an input of said optional circuit; c.unidirectional conductor means having an input connected to said signalterminal and having a gate; and d. circuit means for setting theconduction state of said unidirectional conductor means, said circuitmeans comprising:i. a coupling node coupled to said signal terminalthrough said unidirectional conductor means; and ii. a feedback nodecoupled to said gate of said unidirectional conductor means;wherein,said conduction state of said unidirectional conductor means is set inaccordance with a potential difference between said coupling node andsaid feedback node; and wherein, potential variation at said gate ofsaid unidirectional conductor means has the same phase as potentialvariation at said coupling node so that a circuit loop including thesignal path of said coupling node and said feedback node forms apositive feedback loop.
 3. A multifunctional terminal circuit,comprising:a. an optional circuit; b. a signal terminal connected to aninput of said optional circuit; c. unidirectional conductor means alsoconnected to said signal terminal; and d. circuit means, having acoupling node coupled to said signal terminal through saidunidirectional conductor means, for setting the conduction state of saidundirectional conductor in accordance with a potential differencebetween said signal terminal and said coupling node, said circuit meanscomprising:i. a first circuit operable to connect said coupling node toa first potential; and ii. a second circuit connected to said couplingnode;wherein, when said first circuit operates to connect said couplingnode to said first potential, said unidirectional conductor means is ina non-conducting state and said second circuit is activated with saidfirst potential, and when said first circuit does not so connect saidcoupling node to said first potential, said unidirectional conductormeans conducts in accordance with said potential difference between saidsignal terminal and said coupling node, and said second circuit isactivated with a given potential which corresponds to the potentialapplied to said signal terminal.
 4. A multifunction terminal circuit,according to claim 3, wherein said second circuit includes a volatilememory device which, when said unidirectional conductor means is in anon-conducting state, is power-supplied with said first potential and,when said unidirectional conductor means is in a conducting state, ispower-supplied with a potential applied to said signal terminal, so thatsaid volatile memory device is always activated by either said firstpotential or said potential applied to said signal terminal.
 5. Amultifunction terminal circuit, according to claim 1, 2, 3 or 4, whereinsaid optional circuit includes an electrically programmable read-onlymemory, and the signals applied to said signal terminal include aprogramming signal; and wherein, when said unidirectional conductormeans is in a conducting state, upon reception of said programmingsignal said circuit means receives said programming signal through saidunidirectional conductor means and provides a program instruction tosaid optional circuit in order to execute programming of saidelectrically programmable read-only memory.
 6. A multifunctionalterminal circuit, according to claim 1, 2, 3 or 4, wherein saidunidirectional conductor means includes a P-N junction device connectedbetween said signal terminal and said coupling node of said circuitmeans, and wherein the threshold voltage of said P-N junction determinessaid potential difference between said signal terminal and said couplingnode at which said unidirectional conductor means is in a conductingstate.
 7. A multifunction terminal circuit, according to claim 1, 2, 3or 4, wherein said unidirectional conductor means includes anenhancement-type MOS transistor having a gate and first and secondelectrodes, with said gate connected to said first electrode, said firstand second electrodes connected between said signal terminal and saidcoupling node of said circuit means, and wherein the gate-thresholdvoltage of said MOS transistor determines said potential differencebetween said signal terminal and said coupling node at which saidunidirectional conductor means is in a conducting state.
 8. Amultifunction terminal circuit, according to claim 3, wherein saidsecond circuit includes a three-state buffer.
 9. A multifunctionterminal circuit, comprising:a. an electrically programmable read-onlymemory; b. a signal terminal connected to an input of said electricallyprogrammable read-only memory; c. a first MOS transistor ofenhancement-type having first and second ends, a gate, a drain, and asource, with said first end connected to said signal terminal, said gatecoupled to said drain, and the drain-source path of said first MOStransistor connected between said first and second ends of said firstMOS transistor; d. a second MOS transistor having first and second ends,a gate, a drain, and a source, with said first end thereof connected toa first potential, said second end thereof connected to said second endof said first MOS transistor, the drain-source path of said second MOStransistor being connected between said first and second ends of saidsecond MOS transistor, and said second end of said second MOS transistorbeing defined as a coupling node; e. a third MOS transistor ofdepletion-type having first and second ends, a gate, a drain, and asource, with said first end thereof connected to said coupling node,said gate thereof coupled to said source thereof, the drain-source pathof said third MOS transistor connected between said first and secondends of said third MOS transistor, and said second end of said third MOStransistor being defined as an output node; and f. a fourth MOStransistor having first and second ends, a gate, a drain, and a source,with said first end thereof connected to said output node, said secondend thereof connected to a fixed potential, and the drain-source path ofsaid fourth MOS transistor connected between said first and second endsof said fourth MOS transistor.
 10. A multifunction terminal circuit,comprising:a. a signal circuit including a central progressing unit; b.a signal terminal connected to an input of said signal circuit; c. afirst MOS transistor of enhancement-type having first and second ends, agate, a source, and a drain, with said first end connected to saidsignal terminal, said gate coupled to said drain, and the drain-sourcepath of said first MOS transistor connected between said first andsecond ends of said first MOS transistor; d. a second MOS transistor ofenhancement-type having first and second ends, a gate, a source, and adrain, with said first end thereof connected to a first potential, andsaid second end thereof connected to said second end of said first MOStransistor, said gate of said second MOS transistor coupled to saiddrain thereof, the drain-source path of said second MOS transistorconnected between said first and second ends of said second MOStransistor, and said second end of said second MOS transistor having apower supply input and being defined as a coupling node; and e. avolatile memory device connected at said power supply input to saidcoupling node.
 11. A multifunction terminal circuit, comprising:a. anoptional circuit; b. a signal terminal connected to an input of saidoptional circuit; c. unidirectional conductor means also connected tosaid signal terminal; and d. circuit means, having a coupling nodecoupled to said signal terminal through said unidirectional conductormeans, for setting the conduction state of said unidirectional conductormeans in accordance with a potential difference between said signalterminal and said coupling node;wherein, said unidirectional conductormeans includes: i. a MOS transistor having a gate and first and secondelectrodes, with said first and second electrodes being connectedbetween said signal terminal and said coupling node of said circuitmeans; and ii. potential divider means for dividing a potential at saidcoupling node and providing a divided potential to said gate of said MOStransistor.
 12. A multifunction terminal circuit, comprising:a. anoptional circuit; b. a signal terminal connected to an input of saidoptional circuit; c. a first conductivity enhancement-type first MOStransistor having a gate, a source electrode, and a drain electrode,with said drain electrode and said gate connected to said signalterminal, and with said source electrode thereof defined as a couplingnode; d. a second conductivity enhancement-type second MOS transistorhaving source and drain electrodes, with said source electrode thereofconnected to a first potential and said drain electrode thereofconnected to said source electrode of said first MOS transistor; and e.a C-MOS inventer having a power supply path connected between saidcoupling node and ground;wherein the conduction state of said first MOStransistor is determined in accordance with the potential differencebetween said signal terminal and said coupling node.
 13. A multifunctionterminal circuit, comprising:a. an optional circuit; b. a signalterminal connected to said optional circuit; c. a first conductivityenhancement-type first MOS transistor having a gate, a source electrode,and a drain electrode, with said source electrode connected to saidsignal terminal; d. a first circuit, an output end of which, beingdefined as a coupling node, is coupled with said gate of said first MOStransistor; and e. a second conductivity enhancement-type second MOStransistor having a gate, a source electrode, and a drain electrode,with said source electrode thereof grounded, said gate thereof connectedto said coupling node, and said drain electrode thereof connected tosaid drain electrode of said first MOS transistor;wherein, said firstand second MOS transistors form a C-MOS inverter having an inputconnected to said coupling node and an output delivered from said drainelectrode of said second MOS transistor; and wherein the conductionstate of said first MOS transistor is determined in accordance with apotential difference between said signal terminal and said couplingnode.